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? semiconductor components industries, llc, 2011 january, 2011 ? rev. 16 1 publication order number: nbsg14/d nbsg14 2.5v/3.3v?sige differential 1:4 clock/data driver with rsecl* outputs *reduced swing ecl description the nbsg14 is a 1 ? to ? 4 clock/data distribution chip, optimized for ultra ? low skew and jitter. inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), lvttl, lvcmos, cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. all outputs loaded with 50 to v cc ? 1.5 v for bga package and v cc ? 2 v for qfn package. features ? maximum input clock frequency up to 12 ghz typical ? maximum input data rate up to 12 gb/s typical ? 30 ps typical rise and fall times ? 125 ps typical propagation delay ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.465 v ? rsecl output level (400 mv peak ? to ? peak output), differential output ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, and lvel devices ? pb ? free packages are available a = assembly location l = wafer lot y = year w = work week = pb ? free package fcbga ? 16 ba suffix case 489 marking diagrams* qfn ? 16 mn suffix case 485g http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information (note: microdot may be in either location) sg 14 alyw 16 sg 14 alyw 1 ?? ?? ?? 1
nbsg14 http://onsemi.com 2 figure 1. bga ? 16 pinout (top view) vtclk clk clk vee vtclk q0 vee q3 q3 q2 vcc vcc q0 q1 q1 q2 a b c d 1234 v ee q3 q3 v cc v ee q0 q0 v cc q1 q1 q2 q2 vtclk clk clk vtclk 5678 16 15 14 13 12 11 10 9 1 2 3 4 nbsg14 exposed pad (ep) figure 2. qfn ? 16 pinout (top view) table 1. pin description pin name i/o description bga qfn d1 1 vtclk ? internal 50 termination pin. see table 2. c1 2 clk ecl, cml, lvcmos, lvds, lvttl input inverted differential input. internal 75 k to v ee and 36.5 k to v cc . b1 3 clk ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. internal 75 k to vee. a1 4 vtclk ? internal 50 termination pin. see table 2. b2,c2 5,16 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guarantee proper operation. a2* 6 q3 rsecl output inverted differential output 3. typically terminated with 50 to v tt = v cc ? 2 v* a3* 7 q3 rsecl output noninverted differential output 3. typically terminated with 50 to v tt = v cc ? 2 v* b3,c3 8,13 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation. a4* 9 q2 rsecl output inverted differential output 2. typically terminated with 50 to v tt = v cc ? 2 v* b4* 10 q2 rsecl output noninverted differential output 2. typically terminated with 50 to v tt = v cc ? 2 v* c4* 11 q1 rsecl output inverted differential output 1. typically terminated with 50 to v tt = v cc ? 2 v* d4* 12 q1 rsecl output noninverted differential output 1. typically terminated with 50 to v tt = v cc ? 2 v* d3* 14 q0 rsecl output inverted differential output 0. typically terminated with 50 to v tt = v cc ? 2 v* d2* 15 q0 rsecl output noninverted differential output 0. typically terminated with 50 to v tt = v cc ? 2 v* n/a ? ep ? the exposed pad (ep) and the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is not electrically connected to the die but may be electrically and thermally connected to v ee on the pc board. 1. in the differential configuration when the input termination pins (vtclk, vtclk ) are connected to a common termination voltage, if no signal is applied then the device will be susceptible to self ? oscillation. *devices in bga package typically terminated with 50 to v tt = v cc ? 1.5 v.
nbsg14 http://onsemi.com 3 50 50 vtclk clk clk vtclk v ee v cc figure 3. logic diagram 75 k 75 k 36.5 k q3 q3 q2 q2 q1 q1 q0 q0 table 2. interfacing options interfacing options connections cml connect vtclk and vtclk to v cc lvds connect vtclk and vtclk together ac ? coupled bias vtclk and vtclk inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage (v thr ) should be applied to the unused differential input. nominal v thr is 1.5 v for lvttl and v cc /2 for lvcmos inputs. this voltage must be within the v thr specification. table 3. attributes characteristics value value internal input pulldown resistor (clk, clk ) 75 k internal input pullup resistor (clk ) 36.5 k esd protection human body model machine model > 2 kv > 100 v moisture sensitivity (note 1) pb pkg pb ? free pkg fcbga ? 16 qfn ? 16 level 3 level 1 level 3 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 158 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
nbsg14 http://onsemi.com 4 table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ? 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ? 3.6 v v v inpp differential input voltage |clk ? clk | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range fcbga ? 16 qfn ? 16 ? 40 to +70 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 2) 0 lfpm 500 lfpm 0 lfpm 500 lfpm fcbga ? 16 fcbga ? 16 qfn ? 16 qfn ? 16 108 86 41.6 35.2 c/w c/w c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 2) 2s2p (note 3) fcbga ? 16 5 4.0 c/w c/w t sol wave solder pb pb ? free 225 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. jedec standard 51 ? 6, multilayer board ? 2s2p (2 signal, 2 power). 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nbsg14 http://onsemi.com 5 table 5. dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 4) symbol characteristic ? 40 c 25 c 70 c(bga)/85 c(qfn)** unit min typ max min typ max min typ max i ee negative power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 5) 1525 1575 1625 1550 1610 1650 1575 1635 1675 mv v outpp output amplitude voltage 315 405 495 315 405 495 315 405 495 mv v ih input high voltage (single ? ended) (notes 7 and 9) v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc mv v il input low voltage (single ? ended) (notes 8 and 9) v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 mv v thr input threshold voltage (single ? ended) (note 9) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv v ihcmr input high voltage common mode range (differential configuration) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 80 150 80 150 80 150 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. **the device packaged in fcbga ? 16 have maximum temperature specification of 70 c and devices packaged in qfn ? 16 have maximum temperature specification of 85 c. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to ? 0.5 v. 5. all outputs loaded with 50 to v cc ? 1.5 v for bga package and v cc ? 2 v for qfn package. v oh /v ol measured at v ih /v il (typical). 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 8. v il always v ee . |v il ? v thr | < 2600 mv. 9. v thr is the voltage applied to one input when running in single ? ended mode.
nbsg14 http://onsemi.com 6 table 6. dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 10) symbol characteristic ? 40 c 25 c 70 c(bga)/85 c(qfn)** unit min typ max min typ max min typ max i ee negative power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 11) 2325 2375 2425 2350 2410 2450 2375 2435 2475 mv v outpp output amplitude voltage 350 440 530 350 440 530 350 440 530 mv v ih input high voltage (single ? ended) (notes 13 and 15) v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc mv v il input low voltage (single ? ended) (notes 14 and 15) v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 mv v thr input threshold voltage (single ? ended) (note 15) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv v ihcmr input high voltage common mode range (differential configuration) (note 12) 1.2 3.3 1.2 3.3 1.2 3.3 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 80 150 80 150 80 150 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. **the device packaged in fcbga ? 16 have maximum temperature specification of 70 c and devices packaged in qfn ? 16 have maximum temperature specification of 85 c. 10. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ? 0.165 v. 11. all outputs loaded with 50 to v cc ? 1.5 v for bga package and v cc ? 2 v for qfn package. v oh /v ol measured at v ih /v il (typical). 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 13. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 14. v il always v ee . |v il ? v thr | < 2600 mv. 15. v thr is the voltage applied to one input when running in single ? ended mode.
nbsg14 http://onsemi.com 7 table 7. dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v (note 16) symbol characteristic ? 40 c 25 c 70 c(bga)/85 c(qfn)** unit min typ max min typ max min typ max i ee negative power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 17) ? 975 ? 925 ? 875 ? 950 ? 890 ? 850 ? 925 ? 865 ? 825 mv v outpp output amplitude voltage ? 3.465 v v ee ? 3.0 v ? 3.0 v < v ee ? 2.375 v 350 315 440 405 530 495 350 315 440 405 530 495 350 315 440 405 530 495 mv v ih input high voltage (single ? ended) (notes 19 and 21) v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc v cc ? 1435 v cc ? 1000* v cc mv v il input low voltage (single ? ended) (notes 20 and 21) v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 v ih ? 2500 v cc ? 1400* v ih ? 150 mv v thr input threshold voltage (single ? ended) (note 21) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv v ihcmr input high voltage common mode range (differential configuration) (note 18) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@ v ih ) 80 150 80 150 80 150 a i il input low current (@ v il ) 25 100 25 100 25 100 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *typicals used for testing purposes. **the device packaged in fcbga ? 16 have maximum temperature specification of 70 c and devices packaged in qfn ? 16 have maximum temperature specification of 85 c. 16. input and output parameters vary 1:1 with v cc . 17. all outputs loaded with 50 to v cc ? 1.5 v for bga package and v cc ? 2 v for qfn package. v oh /v ol measured at v ih /v il (typical). 18. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 19. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 20. v il always v ee . |v il ? v thr | < 2600 mv. 21. v thr is the voltage applied to one input when running in single ? ended mode.
nbsg14 http://onsemi.com 8 table 8. ac characteristics for fcbga ? 16 v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbol characteristic ? 40 c 25 c 70 c unit min typ max min typ max min typ max f max maximum frequency (see figure 4) (note 22) 10.7 12 10.7 12 10.7 12 ghz t plh , t phl propagation delay to output differential 100 125 150 100 125 150 100 125 150 ps t skew duty cycle skew (note 23) within ? device skew (note 24) device ? to ? device skew (note 25) 2 6 25 10 15 50 2 6 25 10 15 50 2 6 25 10 15 50 ps t jitter rms random clock jitter (figure 4) (note 27) f in < 10 ghz peak ? to ? peak data dependent jitter (note 28) f in < 10 gb/s 0.2 10 1 0.2 10 1 0.2 10 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 26) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times q, q (20% ? 80%) @ 1 ghz 20 30 55 20 30 55 20 30 55 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 22. measured using a 500 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc ? 1.5 v. input edge rates 40 ps (20% ? 80%). 23. see figure 6. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 24. within ? device skew is measured between outputs under identical transitions and conditions on any one device. 25. device ? to ? device skew for identical transitions at identical v cc levels. 26. v inpp (max) cannot exceed v cc ? v ee (applicable only when v cc ? v ee < 2600 mv). 27. additive rms jitter with 50% duty cycle clock signal at 10 ghz. 28. additive peak ? to ? peak data dependent jitter with nrz prbs 2 31 ? 1 data at 10 gb/s.
nbsg14 http://onsemi.com 9 table 9. ac characteristics for qfn ? 16 v cc = 0 v; v ee = ? 3.465 v to ? 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum frequency (see figure 4) (note 29) 10.5 12 10.5 12 10.5 12 ghz t plh , t phl propagation delay to output differential 90 125 160 90 125 160 90 125 160 ps t skew duty cycle skew (note 30) within ? device skew (note 31) device ? to ? device skew (note 32) 3 6 25 15 15 50 3 6 25 15 15 50 3 6 25 15 15 50 ps t jitter rms random clock jitter (figure 4) (note 34) f in < 10 ghz peak ? to ? peak data dependent jitter (note 35) f in < 10 gb/s 0.2 1 0.2 10 1 0.2 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 33) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times q, q (20% ? 80%) @ 1 ghz 15 30 55 20 30 55 20 30 55 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 29. measured using a 500 mv source, 50% duty cycle clock source. all outputs loaded with 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%) 30. see figure 6. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 31. within ? device skew is measured between outputs under identical transitions and conditions on any one device. 32. device ? to ? device skew for identical transitions at identical v cc levels. 33. v inpp (max) cannot exceed v cc ? v ee (applicable only when v cc ? v ee < 2600 mv). 34. additive rms jitter with 50% duty cycle clock signal at 10 ghz. 35. additive peak ? to ? peak data dependent jitter with nrz prbs 2 31 ? 1 data at 10 gb/s.
nbsg14 http://onsemi.com 10 ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? ??????? ??????? ??????? output p ? p spec (amplitude guarantee) figure 4. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) at ambient temperature (typical) 0 100 200 300 400 500 123456789101112 input frequency (ghz) output voltage amplitude (mv) jitterout ps (rms) ???? ???? figure 5. eye diagram at 10.8 gbps (v cc ? v ee = 3.3 v @ 25 c with input data pattern of 2^31 ? 1 prbs. total pk ? pk system jitter including signal generator is 18 ps. this data was taken by acquiring 7000 waveforms.) x = 17 ps/div, y = 53 mv/div
nbsg14 http://onsemi.com 11 t phl figure 6. ac reference measurement d /clk d/clk q q t plh v inpp = = v ih (clk) ? v il (clk) v outpp = v oh (q) ? v ol (q) figure 7. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 1.5 v (bga) v tt = v cc ? 2.0 v (qfn) ordering information device package shipping ? nbsg14bahtbg fcbga ? 16 (pb ? free) 100 / tape & reel nbsg14bar2 fcbga ? 16 100 / tape & reel (contact sales representative) nbsg14mn qfn ? 16 123 units / rail NBSG14MNG qfn ? 16 (pb ? free) 123 units / rail nbsg14mnr2 qfn ? 16 3000 / tape & reel nbsg14mnr2g qfn ? 16 (pb ? free) 3000 / tape & reel nbsg14mnhtbg qfn ? 16 (pb ? free) 100 / tape & reel board description nbsg14baevb nbsg14ba evaluation board ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nbsg14 http://onsemi.com 12 package dimensions fcbga ? 16 ba suffix plastic 4x4 (mm) bga flip chip package case 489 ? 01 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view m ? m e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k ? x ? ? y ? m m ? z ?
nbsg14 http://onsemi.com 13 package dimensions ??? ??? ??? case 485g ? 01 issue e 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nbsg14/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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